1. Field of the Invention
The present invention relates to a test method and a test apparatus for a semiconductor device for use in a process of manufacturing the semiconductor device.
2. Description of the Related Art
In a process of manufacturing a semiconductor device, due to tests being carried out with respect to the semiconductor device, the characteristics/reliability of the semiconductor device are ensured. FIG. 2 shows the flow of the process of manufacturing a semiconductor device. As shown in FIG. 2, tests are carried out during the manufacturing process. These tests can be broadly divided into a visual defect detection for a semiconductor device in a process of forming a large number of semiconductor devices at respective chip regions on a semiconductor wafer, an electrical characteristics test for a semiconductor device formed by packaging the chips which are sectioned out of the semiconductor wafer and on which the large number of semiconductor devices are formed, and a reliability test which is carried out finally.
The visual defect detection is composed of a wafer visual detection, a dust detection, a crystal defect detection, and the like, and is usually carried out about five times with respect to a wafer on which a pattern is formed by, for example, photo etching process (PEP). A problem in appearance such as an abnormality in processing of a pattern, or the like, the presence of dust, defects such as a crystal defect or the like are detected by a defect detection unit. When there is an abnormality (for example, a given number or more of defects arise, or the like) in the detected data, it is dealt with it by a countermeasure in which the products are diced and thrown away in wafer units or lot units, or the presence of an abnormality in a manufacturing apparatus is inspected and restored.
The electrical characteristics test is an test which is carried out with respect to the chips having a large number of semiconductor devices formed thereon and a semiconductor device formed by packaging the chips, and the presence of an operating abnormality in the respective elements is detected by inspecting the operations of the respective elements while varying various electrical parameters. Only the semiconductor devices which are determined to be non-defective products here are provided to the next process.
Moreover, the reliability test is for detecting the presence of an operating abnormality in the respective devices by inspecting the operations of the respective devices while varying various reliability parameters, and for detecting the presence of an abnormality in appearance of the respective devices, with respect to the packaged semiconductor devices. Then, only the semiconductor devices which are determined to be non-defective products here are shipped to market.
In this way, a determination on the non-defect/defect is carried out for each semiconductor device by the electrical characteristics test and the reliability test. However, as the relationship between the test rate and the test time of the electrical characteristics test is shown in FIG. 15, because the test time materially increases when an test rate of the semiconductor device is over 95% with respect to each semiconductor device, as a practical matter, the tests are carried out with respect to about 95% of the semiconductor devices. Therefore, there has been some possibility in which semiconductor devices including semiconductor devices having an abnormality among 5% of the semiconductor devices which are not inspected are shipped, and market defective accidents arise. Further, in the case of a bipolar IC or the like, there has been the problem that an operating abnormality arises only in cases of restricted test parameters (input current, voltage, frequency, temperature, and the like).
Various methods for efficiently carrying out tests at a high accuracy have been studied before now. For example, there have been proposed a method in which an attempt is made to make a foreign matter detection efficient as in Jpn. Pat. Appln. KOKAI Publication No. 10-313026, and a method in which an attempt is made to improve a testing efficiency by using low quality information on a wafer and a mask as in Jpn. Pat. Appln. KOKAI Publication 2001-318151. However, these do no more than improve an test efficiency, and do not reflect the evaluations thereof to evaluations as non-defective product chips, and do not suppress the outflow of defective product chips.